The present invention relates to a method of manufacturing a memory device on a semiconductor substrate. The present invention has particular applicability in manufacturing nonvolatile semiconductor memory devices requiring a high-quality dielectric layer between a floating gate and a control gate.
Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (flash EEPROMs), typically comprise a floating gate memory cell which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. A voltage differential is created in the cell when a high voltage is applied to the control gate while the channel region is kept at a low voltage. This voltage difference causes electrons to move from the channel region to the floating gate through a phenomenon known as tunneling, thus charging the floating gate. This movement of electrons is referred to as programming.
FIG. 1 depicts a typical flash memory cell, wherein a pair of source/drain regions 20 and a channel region 30 are formed in a semiconductor substrate 10. A floating gate 50 is formed, usually of polysilicon, above the channel region 30, with a tunnel oxide layer 40 in between. A dielectric film 60, known as an xe2x80x9cONO layerxe2x80x9d comprising a bottom silicon oxide layer 61, a silicon nitride layer 62 and a top silicon oxide layer 63, is typically formed on top of the floating gate 50. After formation of the top oxide layer 63, it is cleaned, as by chemical cleaning, typically employing an acid or by plasma techniques. A polysilicon control gate 70 is then formed on top oxide layer 63, followed by formation of a tungsten silicide (WSi) contact layer 80.
The top oxide layer 63 is typically relatively thin, for example, about 55 xc3x85 or less, and becomes even thinner due to the chemical cleaning procedure. If the top oxide layer is thinned excessively, the distance between the floating gate 50 and the subsequently formed control gate 70 is sufficiently reduced to adversely affect the performance of the finished device, particularly the xe2x80x9cdata retentionxe2x80x9d of the flash memory; i.e., the length of time the floating gate 50 is able to store a charge. Data retention is a function of the thickness of the ONO film 60. The current industry standard for data retention of a flash memory cell is 100,000 hours (about 11.4 years). However, if the top oxide layer 63 is reduced by greater than about 10% below the design rule for the semiconductor device, leakage will occur from the floating gate 50 to the control gate 70, thereby decreasing device data retention below the standard. Thus, the tolerance for error in the processing of the top oxide layer 63 (its xe2x80x9cprocess windowxe2x80x9d), especially during the cleaning process, is extremely narrow.
Furthermore, the problem of excessive thinning of the top oxide 63 becomes even more critical on scaling the device to smaller dimensions, in response to the increasing demand for miniaturization of electronic components and reduction of the power requirements of flash memory devices. As the flash memory is scaled down, and the thickness of the ONO film 60 is correspondingly reduced, deposition of its component oxide layers 61, 63 is more difficult to control due to inherent limitations of the deposition process, which results in oxide layers of lesser quality.
There exists a need for a method of manufacturing a composite dielectric layer of a flash memory device without reducing the data retention of the finished device below design requirements. There also exists a continuing need for a method of manufacturing a composite interpoly dielectric layer with improved control and greater accuracy.
An advantage of the present invention is a method of manufacturing a composite interpoly dielectric layer of a nonvolatile semiconductor memory device without reducing device performance.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device having a floating gate formed on a channel region of a semiconductor substrate and a control gate formed above the floating gate spaced apart from the floating gate a distance corresponding to at least a minimum design data retention, which method comprises depositing a first oxide dielectric layer on the floating gate at a first thickness; depositing a nitride dielectric layer on the first oxide dielectric layer at a second thickness; depositing a second oxide dielectric layer on the nitride dielectric layer at a third thickness; cleaning the second oxide dielectric layer, thereby reducing the third thickness to a fourth thickness less than the third thickness; and forming the control gate on the second oxide dielectric layer having the fourth thickness.
Another aspect of the present invention is a method of manufacturing a semiconductor device, which method comprises forming a tunnel oxide layer on a channel region in a semiconductor substrate; forming a polysilicon floating gate on the tunnel oxide layer, depositing a silicon dioxide layer on the floating gate at a first thickness; depositing a silicon nitride layer on the silicon dioxide layer at a second thickness; depositing an oxide layer having a dielectric constant greater than silicon dioxide at a third thickness; chemically cleaning the oxide layer, thereby reducing the third thickness to a fourth thickness less than the third thickness; and forming a polysilicon control gate on the oxide layer; wherein: the sum of the first, second and fourth thicknesses corresponds to at least a minimum design data retention; and the silicon oxide layer, silicon nitride layer and oxide layer have a combined capacitance corresponding to the design rule of the semiconductor device.
A still further aspect of the present invention is a semiconductor device comprising a tunnel oxide layer on a channel region of a semiconductor substrate;
a floating gate on the tunnel oxide layer; a control gate formed above the floating gate and spaced apart from the floating gate at least a predetermined distance; and a composite dielectric layer between the control gate and the floating gate, the dielectric layer comprising: a first oxide layer on the floating gate, the first oxide layer having a first thickness; a nitride layer on the first oxide layer, the nitride layer having a second thickness; and a second oxide layer having a dielectric constant about equal to or greater than 10 and having a third thickness; wherein the sum of the first, second and third thicknesses corresponds to at least a minimum design data retention; and wherein the first and second oxide layers and the nitride layer have a combined capacitance corresponding to the design rule of the semiconductor device.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.